The use of distributed computing systems, in which multiple separate computers perform computation problems or information processing, is becoming increasingly widespread. In distributed computing systems for enterprise applications, banks or arrays of data storage devices are commonly employed to facilitate large-scale data storage for a plurality of hosts or users. Because latency is a significant issue in such computing systems, solid-state drives (SSDs) are commonly used as data storage devices, since data can be written to and read from the flash memory cells typically used in an SSD very quickly. Furthermore, solid-state memory technologies currently under development, such as TLC flash (with three bits per cell) and QLC flash (with four bits per cell) have the potential to further improve the performance, cost, and energy efficiency of SSDs.
However, in addition to improved performance, TLC flash, QLC flash, and the like are generally subject to higher bit-error rates. Consequently, SSDs that include these solid-state memory technologies may employ more robust error-correcting code (ECC) methods, for example low-density parity-check (LDPC) code. Unfortunately, such ECC methods typically include complex algorithms that generally increase latency and are implemented with larger circuits that increase the cost and power consumption of an SSD.